SYNTHESIS FOR MULTI-MODE TIMING CLOSURE
4 September 2008
Azuro, Inc. the provider of advanced clock implementation tools for nanometer chip design, today announced that NXP Semiconductor has adopted Azuro's PowerCentric clock-tree synthesis (CTS) and optimization solution. NXP's MultiMarket Semiconductor business unit adopted PowerCentric after demonstrating a significant reduction in clock power while improving the clock timing.
"Our group is faced with some very challenging clock structures that need to be balanced across multiple operating modes. We are also under constant pressure to reduce power," said Arvind Chopra, Design Manager for NXP Semiconductors. "PowerCentric is a well-integrated solution that gives us better timing results and much faster timing closure. It also provides significant power savings which we found correlated well with actual silicon results."
NXP found PowerCentric's multi-mode clock balancing capability sharply reduced the time and effort needed to implement the clocks simultaneously across all modes. Not only was the process much more automated, it also produced a tree with significantly smaller insertion delay. A critical requirement needed to close the design timing was PowerCentric's ability to optimize the setup and hold timing concurrently with CTS. PowerCentric achieved its power savings by adding new clock gates to the design without significantly impacting the total cell area.
"NXP's products have sophisticated timing schemes that make CTS a key factor in their ability to meet performance goals and market window opportunities," said Paul Cunningham, co-founder and chief executive officer of Azuro. "PowerCentric's unique technology helps our customers to sharpen their product differentiation and to speed-up their design time."
